Analog VLSI Implementation of Novel Hybrid Neural Network Multiplier Architecture

Neural networks are suitable to resolve problems where conventional resolution methods fail. The multipliers form a basic and important block in realising a neural network and this is commonly known as “Synapse”. Their roles are to multiply an input current with trained digital weights. Several research attempts to implement synapses. Some use numeric implementation whereas others use analogue circuit. Each of these implementations methods has its own advantages and drawbacks. Numeric multipliers are very suitable for applications that need high accuracy and precision results. Unfortunately it occupies a considerable silicon area. Analogue synapses are efficient-silicon area and are able to operate at high frequency. However synaptic weights are badly saved in their analogue form. To combine the advantages of these two implementation methods, a mixed implementation technique provides best performances. A mixed synapse named multiplier digital-to analogue converter (MDAC) is a multiplier bloc that multiplies an analogue reference by a binary coded synaptic weight .Current steering MDAC is the aim of this work for its capability to drive considerable charges at the output of synapses The focus of the present thesis is on the Analog implementation of hybrid multiplier architecture where in a current is multiplied along with the digital weights. The Synapse or the multiplier includes 3 subcomponents: DAC, current steering circuits, and a current mirror circuit.The design of the Synapse is carried out in CADENCE VIRTUOSO and verified. The circuit is tested for its performance with respect to accuracy and power. The functionality of the design is verified using AVAN WAVES. The layout is realised for the same along with the RC extracted view and also the GDSII for the proposed design is extracted. The INL and DNL of the MDAC is found to be 0.5LSB and 0.8LSB respectively, The area occupied is 176.4μm2.The MDAC is monotonic.